An Optimized Architecture for Adaptive Digital Filter: Advanced Study

In this paper, we propose an efficient adaptive FIR filter architecture using a single multiplier and
adder irrespective of number taps using the concept of time sharing multiplier architecture. For
efficient optimization of multiplier architectures, Output Product Coding and parallel pipelined
multiplier are applied. The proposed Adaptive FIR filter architecture is implemented for 32-tap using
Verilog and synthesized using XILINX VIRTEX-5 FPGA device. The results are validated using FPGA
in Loop (FIL), where simulation is done using MATLAB/Simulink-xPC target tool box. This design
provides substantial area reduction compared to the conventional Adaptive FIR filter architectures for
the FPGA implementation. The proposed Adaptive FIR filter supports up to 323 MHz input sampling
frequency for FPGA implementation.